1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the semiconductor device, and more particularly to a semiconductor device and a method for fabricating the semiconductor device, wherein the semiconductor device has each of its bare chips packaged in a so-called CSP (i.e., Chip Size Package) which is substantially equivalent in size to the bare chip.
2. Description of the Related Art
Heretofore, it has been known to provide a so-called MCM (i.e., Multi Chip Module) which is used in constructing a small-sized computer system used in processing various types of information, wherein the MCM is produced by connecting a plurality of LSIs (i.e., Large Scale Integrated circuits) such as memories, microprocessors and the like to a common wiring substrate.
It is impossible for the MCM described above to fulfill a need for the MCM to be reduced in size because the MCM has its packaging area size increased due to the presence a number of passive elements such as chips, resistors, chip capacitors and the like which are different from each other in characteristics and function and is two-dimensionally mounted on the wiring substrate.
On the other hand, in recent years, a so-called CSP, i.e., Chip Size Package which is a microstructure package has been developed. This CSP has a construction in which the bare chip is wrapped up in a wiring built-in insulation film so that a package substantially similar in size to the bare chip is constructed.
For example, in Japanese Laid-Open Patent Application No. Hei8-335663 (hereinafter referred to as the prior art document) disclosed therein is a CSP 71 substantially similar to the above-mentioned CSP; as shown in FIG. 18, in this conventional CSP 71, wrapped up in a wiring built-in insulation film 72 is a bare chip 73 with its circuit side 73B down with the exception of a central portion of an upper surface 73A of the bare chip 73, wherein the wiring built-in insulation film 72 is made of polyimide. Further, the central portion of the upper surface 73A of the bare chip 73 is sealed up by means of an insulating resin 74A. On the other hand, the circuit side 73B of the bare chip 73 is bonded to the wiring built-in insulation film 72 by means of another insulating resin 74B.
In addition, a solder ball 75 corresponding to a pad electrode provided in the circuit side 73B of the bare chip 73 is formed in a lower surface of the wiring built-in insulation film 72. This solder ball 75 is used as a connection electrode when the bare chip 73 is connected with the wiring substrate. Further, in a peripheral portion of an upper surface of the wiring built-in insulation film 72, there is formed a test pad 77 corresponding to the pad electrode of the bare chip 73.
This test pad 77 is brought into electric contact with an inspection probe when the bare chip 73 is examined in its characteristics.
Further, as shown in FIG. 19, the prior art document mentioned above discloses a semiconductor device 79 having a construction in which a plurality of, for example, four pieces of the CSPs 71 shown in FIG. 18 are stacked together on the wiring substrate to have their electrodes connected with each other. The above construction is employed to improve the semiconductor device in packaging density by utilizing a space over the conventional semiconductor device as an additional packaging space of the semiconductor device. In a conventional method for fabricating the semiconductor device thus improved in packaging density: the CSP 71 which is wrapped in the wiring built-in insulation film and located in a first layer is connected with the wiring substrate 78 through a heating and melting process; and, each of the remaining three pieces of the CSPs 71, which are located in a second, third and a fourth layer, respectively, is subsequently connected in a manner similar to the above. In another possible conventional method for fabricating the semiconductor device, the four pieces of these CSPs 71 shown in FIG. 19 are previously positioned as a whole, and subjected to the heating and melting process.
However, in the former of the above conventional methods, though there is substantially no problem as to misalignment of the electrodes in connection, it is necessary to perform a plurality of connection operations; the number of which is equal to the number of the CSPs 71 to be connected. Further, in this case, the bare chip 73 is subjected to thermal stress, which often impairs the bare chip 73 in its characteristics. On the other hand, in the latter of the above conventional methods, when a plurality of the CSPs 71 are stacked together to have their electrodes connected with each other and are subjected to a heating and melting process, misalignment of the CSPs 71 occurs together with flattening of a solder bump in a connection portion of a lower one of the CSPs 71, by means of an upper one of the CSPs 71, to cause a short between the electrodes. Occurrence of such a short decreases the semiconductor device in yield in production and reliability in fabrication thereof.
Problems to be solved by the present invention are as follows. Namely, in the conventional semiconductor device described above, when a plurality of the CSPs are stacked together, it is necessary to stack them one by one. This causes connecting conditions of external electrodes of the upper and the lower one of the CSPs with each other to be unstable, and, therefore decreases the conventional semiconductor device in reliability in connection.
In other words, when a plurality of the CSPs are stacked together, it is necessary to perform a packaging operation while the external electrodes of the lower one of the CSPs are connected with the corresponding external electrodes of the upper one of the CSPs. However, when the number of the layers in which the bare chips are located is increased, a positioning or alignment operation of these external electrodes of the upper one and the lower one of the CSPs becomes much more complicated, which makes it difficult to connect the external electrodes to each other without failure.
Further, in view of fabrication of the semiconductor device, stacking these CSPs together is poor not only in packaging efficiency but also in yield in production since the number of necessary process steps increases.
Furthermore, when a plurality of the chips, each of a high integration density and high processing speed type are stacked together in connection into a multi-layer construction, it becomes difficult to disperse the heat generated in each of the thus stacked chips. This considerably increases the temperature of each of the chips to result in a so-called thermal runaway and often in a breakage of each of the chips.